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february 2013 doc id 023660 rev 1 1/38 AN4164 application note steval-isa113v1: 12 v/4 w, 115 khz non-isolated flyback by mirko sciortino introduction this document describes a 12 v-350 ma power supply set in non-isolated flyback topology with the new viper06 offline high voltage converter by stmicroelectronics. the features of the device are: 800 v avalanche rugged power section pwm operation at 115 khz with frequency jittering for lower emi limiting current with adjustable set point onboard soft-start safe auto-restart after a fault condition (overload, short-circuit) sso-10 package moreover, the viper06 does not require a biasing circuit to operate because the ic can be supplied by an internal current generator, therefore saving the cost of the transformers auxiliary winding (self-biasing). if the device is biased through an auxiliary winding or through a diode connected to the output (external biasing), it can reach very low standby consumption (< 50 mw at 265 v ac ). both cases are treated in the present document. the available protection features are: thermal shutdown with hysteresis, delayed overload protection, and open loop failure protection (the last is available only if the ic is externally biased). figure 1. demonstration board image www.st.com
contents AN4164 2/38 doc id 023660 rev 1 contents 1 adapter features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 schematic and bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 testing the board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 typical waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 line/load regulation and output voltage ripple . . . . . . . . . . . . . . . . . . . . . 13 5.3 burst mode and output voltage ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4 efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5 light load performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 functional check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.3 feedback loop failure protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 feedback loop calculation guide lines . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.2 compensation procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 thermal measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9 emi measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10 board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11 conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AN4164 contents doc id 023660 rev 1 3/38 appendix a test equipment and measurement of effi ciency and light load performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 a.1 measuring input power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 12 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
list of tables AN4164 4/38 doc id 023660 rev 1 list of tables table 1. electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. transformer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. output voltage line-load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5. output voltage ripple at no/light load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 6. no load input power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 7. energy consumption criteria for no load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 8. light load performance p out =25 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 9. light load performance p out =50 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 10. p out @ p in =1 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 11. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
AN4164 list of figures doc id 023660 rev 1 5/38 list of figures figure 1. demonstration board image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. v dd waveforms ic externally biased (j1 selected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. v dd waveforms ic self-biased (j1 not selected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. transformer, pin distances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. transformer, electrical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. transformer side view 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. transformer side view 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 9. drain current/voltage at 115 v ac , max. load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 10. drain current/voltage at 230 v ac , max. load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 11. drain current/voltage at 90 v ac , max. load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 12. drain current/voltage at 265 v ac , max. load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 13. line regulation, ic externally biased (j1 selected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 14. line regulation, ic self-biased (j1 not selected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 15. load regulation, ic externally biased (j1 selected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 16. load regulation, ic self-biased (j1 not selected). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 17. output voltage ripple at 115 v ac no load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 18. output voltage ripple at 230 v ac no load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 19. output voltage ripple at 115 v ac 25 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 20. output voltage ripple at 230 v ac 25 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 21. active mode efficiency of the demonstration board and comparison with energy efficiency standards (ic externally biased) . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 22. p in vs. v in at no load and light load; ic externally biased (j1 selected) . . . . . . . . . . . . . . 17 figure 23. p in vs. v in at no load and light load, ic self-biased (j1 not selected) . . . . . . . . . . . . . . . . 17 figure 24. efficiency at p in = 1 w; ic externally biased (j1 selected) . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 25. efficiency at p in = 1 w; ic self biased (j1 not selected) . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 26. p in at p out = 250 mw; ic externally biased (j1 selected) . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 27. p in at p out = 250 mw; ic self biased (j1 not selected) . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 28. soft-start @ startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 29. soft-start @ startup (zoom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 30. olp short-circuit applied: olp tripping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 31. output short-circuit maintained: olp steady-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 32. output short-circuit maintained: olp steady-state (zoom) . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 33. output short-circuit removal and converter restart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 34. feedback loop failure protection: tripping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 35. feedback loop failure protection: steady-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 36. feedback loop failure protection: steady-state, zoom . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 37. feedback loop failure protection: converter restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 38. control loop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 39. thermal measurement at v in = 90 v ac , full load, ic externally biased . . . . . . . . . . . . . . . 26 figure 40. thermal measurement at v in = 115 v ac , full load, ic externally biased . . . . . . . . . . . . . . 26 figure 41. thermal measurement at v in = 230 v ac , full load, ic externally biased . . . . . . . . . . . . . . 27 figure 42. thermal measurement at v in = 265 v ac , full load, ic externally biased . . . . . . . . . . . . . . 27 figure 43. thermal measurement at v in = 90 v ac , iout = 310 ma, ic self biased . . . . . . . . . . . . . . . 27 figure 44. thermal measurement at v in = 115 v ac , iout = 310 ma, ic self biased . . . . . . . . . . . . . . 28 figure 45. thermal measurement at v in = 230 v ac , full load, ic self biased . . . . . . . . . . . . . . . . . . . 28 figure 46. thermal measurement at v in = 265 v ac , full load, ic self biased . . . . . . . . . . . . . . . . . . . 28 figure 47. average measurements at full load, t amb =25 c, 115 v ac , ic externally biased . . . . . . 29
list of figures AN4164 6/38 doc id 023660 rev 1 figure 48. average measurements at full load, t amb =25 c, 230 v ac , ic externally biased . . . . . . . 29 figure 49. board layout - complete . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 50. board layout - top layer + top overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 51. board layout - bottom layer + top overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 52. connection of the uut to the wattmeter for power measurements . . . . . . . . . . . . . . . . . . 33 figure 53. switch in position 1 - setting for standby measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 54. switch in position 2 - setting for efficiency measurements . . . . . . . . . . . . . . . . . . . . . . . . . 34
AN4164 adapter features doc id 023660 rev 1 7/38 1 adapter features the electrical specifications of the demonstration board are listed in ta b l e 1 . table 1. electrical specifications parameter symbol value input voltage range v in [90 v ac ; 265 v ac ] output voltage v out 12 v max. output current i out 0.35 a precision of output regulation v out_lf 5% high frequency output voltage ripple v out_hf 50 mv max. ambient operating temperature t amb (1) 1. see section 2: circuit description 30 c (self biasing) 60 c (external biasing)
circuit description AN4164 8/38 doc id 023660 rev 1 2 circuit description the power supply is set in flyback topology. the schematic is given in figure 2 , and the bill of material in ta bl e 2 . the input section includes a resistor r0 for inrush current limiting, a diode bridge (d0) and a pi filter for emc suppression (cin1, lin, cin2). the transformer core is a standard e13. the output voltage value is set in a simple way through the rfbh-rfbl voltage divider between the output terminal and the fb pin, according to the following formula: equation 1 in fact, the fb pin is the input of an error amplifier and is an accurate 3.3 v voltage reference. in the schematic the upper resistor rfbh has been split into rfbh1 and rfbh2; and the lower resistor rfbl into rfbl1 and rfbl2 in order to allow a better tuning of the output voltage value. the compensation network is connected between the comp pin (which is the output of the error amplifier) and the gnd pin, and is made up of cp, cc and rc. the resistor rlim, placed between the lim and gnd pins, has the purpose of reducing the drain current limitation, from idlim to about 250 ma in order to limit the deliverable output power of the converter and keep safe the power components. at power-up, as the rectified input voltage rises over the v drainstart threshold, the high voltage current generator starts charging the v dd capacitor, cvdd, from 0 v up to v ddon . at this point the power mosfet starts switching, the hv current generator is turned off and the ic is biased by the energy stored in cvdd. in this demonstration board, if the jumper j1 is not selected, the ic is biased through the internal high-voltage startup current generator, which is automatically turned on as the v dd voltage drops down to v ddcson and switched off as v dd is charged up to v ddon (self- biasing). self-biasing is excluded by keeping the v dd pin voltage always above the v dd cson threshold. in this board, since the output voltage is higher than v ddcson , this is obtained by just selecting the jumper j1, which connects the output terminal to the v dd pin through a small signal diode. if the output voltage is lower than v ddcson , the self-biasing can be excluded only using an auxiliary winding. the ic biasing through auxiliary winding or through the output is referred to as external biasing. in figure 3 the v dd waveforms for both cases (ic external biased and self-biased) are shown. the use of self-biasing means higher power dissipation across the ic (which must be avoided if low standby consumption and/or high efficiency is required) and higher ic temperature respect to external biasing (at given ambient temperature, the maximum deliverable output power is lower; or, a lower maximum ambient temperature is required to deliver the same power throughput). for this reason, two different maximum t amb values, in full load condition, are indicated in ta b l e 1 , depending on the selection of weather self biasing or external biasing. these values are confirmed by the thermal measurements reported in section 8 . ? ? ? ? ? ? ? ? + ? = rfbl rfbh v v out 1 3 . 3
AN4164 schematic and bill of material doc id 023660 rev 1 9/38 3 schematic and bill of material figure 2. application schematic d2 comp drain viper06 s h gnd fb lim vdd drain drain drain drain cf ilt2 j1 rf b h1 rf b l1 rf b l2 d au x rlim + cvdd cf ilt1 cf b cp rc cc + cin1 rf b h2 lin - + cin2 ac in vout + co u t t1 - + d0 r0 ac in am1 33 2 8 v1
schematic and bill of material AN4164 10/38 doc id 023660 rev 1 table 2. bill of material ref. part description package manufacturer cin1 2.2 f, 400 v nhg series electrolytic capacitor cin2 4. 7 f, 400 v ax series electrolytic capacitor saxon cvdd 1 f, 50 v electrolytic capacitor 1206 murata cfilt1 100 nf, 50 v ceramic capacitor 0805 cfilt2 not mounted cc 10 nf, 50 v ceramic capacitor 1206 cp 1 nf, 50 v ceramic capacitor 1206 cfb 1 nf, 50 v ceramic capacitor 0805 cout 330 f, 16 v zl series ultra-low esr electrolytic cap. rubycon d0 mb6s 600 v 1 a diode bridge to-269aa vishay d2 stps2h100 100 v, 2 a, power schottky rectifier sma st daux 1n4148w surface mount fast switching diode sod-123 zetex r0 4.7 3/4 w resistor rlim 15 k 5% 1/4 w resistor 0805 rc 47 k 5% 1/4 w resistor 0805 rfbh1 33 k 1% 1/4 w resistor 0805 rfbh2 0 1206 rfbl1 12 k 1% 1/4 w resistor 1206 rfbl2 0.47 k 1% 1/4 w resistor 0805 ic1 viper06hs offline high-voltage pwm controller sso-10 st t1 1921.0040 transformer magnetica lin b82144a2105j 1 mh inductor lbc series epcos figure 3. v dd waveforms ic externally biased (j1 selected) figure 4. v dd waveforms ic self-biased (j1 not selected) am1 33 29v1 am1 333 0v1
AN4164 transformer doc id 023660 rev 1 11/38 4 transformer the characteristics of the transformer are listed in the table below. the following figures show the electrical diagram, size and pin distances (in mm) of the transformer. table 3. transformer characteristics parameter value test conditions manufacturer magnetica part number 1921.0040 primary inductance (pins 3 - 4) 1.2 mh 15% measured at 1 khz 0.1 v leakage inductance 2.8% measured at 10 khz 0.1 v primary to secondary turn ratio (3 - 4)/(5 - 8) 6.11 5% measured at 10 khz 0.1 v primary to auxiliary turn ratio (3 - 4)/(2 - 1) 5 5% measured at 10 khz 0.1 v figure 5. transformer, pin distances figure 6. transformer, electrical diagram am1 333 1v1 am1 333 2v1 figure 7. transformer side view 1 figure 8. transformer side view 2 am1 3333 v1 am1 333 4v1
testing the board AN4164 12/38 doc id 023660 rev 1 5 testing the board 5.1 typical waveforms drain voltage and current waveforms in full load condition are shown for the two nominal input voltages in figure 9 and 10 , and for minimum and maximum input voltage in figure 11 and 12 respectively. figure 9. drain current/voltage at 115 v ac , max. load figure 10. drain current/voltage at 230 v ac , max. load am1 333 5v1 am1 333 6v1 figure 11. drain current/voltage at 90 v ac , max. load figure 12. drain current/voltage at 265 v ac , max. load am1 333 7v1 am1 3338 v1
AN4164 testing the board doc id 023660 rev 1 13/38 5.2 line/load regulation and output voltage ripple the output voltage of the board has been measured in different line and load conditions. the results are shown in ta bl e 4 . the output voltage is practically not affected by the line condition and by the ic biasing (self-biasing or external biasing). table 4. output voltage line-load regulation v in [v ac ] v out [v] no load 50% load 75% load 100% load ic externally biased ic self biased ic externally biased ic self biased ic externally biased ic self biased ic externally biased ic self biased 90 12.04 12.05 12.00 11.98 12.00 11.98 11.99 11.97 115 12.05 12.05 12.00 11.99 12.00 11.98 11.99 11.97 150 12.05 12.05 12.00 11.98 12.00 11.98 11.99 11.97 180 12.05 12.04 12.00 11.98 12.00 11.98 11.99 11.97 230 12.05 12.04 12.00 11.98 12.00 11.98 11.99 11.97 265 12.05 12.04 12.00 11.98 12.00 11.98 11.99 11.97 figure 13. line regulation, ic externally biased (j1 selected) figure 14. line regulation, ic self-biased (j1 not selected) am116 88 v1 11.7 11. 8 11.9 12 12.1 12.2 8 0 105 1 3 0 155 1 8 02052 3 0 255 v out [v] v in [v ac ] 0 25 % 50 % 75 % 100 % am116 8 9v1 11.7 11. 8 11.9 12 12.1 12.2 8 0 105 1 3 0 155 1 8 02052 3 0 255 v out [v] v in [v ac ] 0 25 % 50 % 75 % 100 % figure 15. load regulation, ic externally biased (j1 selected) figure 16. load regulation, ic self-biased (j1 not selected) am11690v1 11.7 11. 8 11.9 12 12.1 12.2 0 0.05 0.1 0.15 0.2 0.25 0. 3 0. 3 50.4 v out [v] i out [a] 90 115 2 3 0 265 am11691v1 11.7 11. 8 11.9 12 12.1 12.2 0 0.05 0.1 0.15 0.2 0.25 0. 3 0. 3 5 0.4 v out [v] i out [a] 90 115 2 3 0 265
testing the board AN4164 14/38 doc id 023660 rev 1 5.3 burst mode and output voltage ripple when the converter is lightly loaded, the comp pin voltage decreases. as it reaches the shutdown threshold, vcompl (1.1 v, typical), the switching is disabled and the energy is not transferred to the secondary side anymore. at this point, the feedback reaction to the stop of the energy delivery makes the comp pin voltage increase again. as it rises 40 mv above the v compl threshold, the normal switching operation is resumed. this results in a controlled on/off operation which is referred to as ?burst mode?. this mode of operation keeps the frequency-related losses low when the load is very light or disconnected, making it easier to comply with energy saving regulations. the figures below show the output voltage ripple when the converter is no/lightly loaded and supplied with 115 v ac and with 230 v ac respectively. figure 17. output voltage ripple at 115 v ac no load figure 18. output voltage ripple at 230 v ac no load am11692v1 am1169 3 v1 figure 19. output voltage ripple at 115 v ac 25 ma figure 20. output voltage ripple at 230 v ac 25 ma am11694v1 am11695v1
AN4164 testing the board doc id 023660 rev 1 15/38 ta b l e 5 shows the measured value of the burst mode frequency ripple measured in different operating conditions. the ripple in burst mode operation is very low. 5.4 efficiency the active mode efficiency is defined as the average of the efficiencies measured at 25%, 50%, 75% and 100% of maximum load, at nominal input voltage (v in = 115 v ac and v in = 230 v ac ). external power supplies (the power supplies are contained in a separate housing from the end-use devices they are powering) need to comply with the code of conduct (version 4.0) ?active mode efficiency? criterion, which states an active mode efficiency higher than 71.18% for a power throughput of 4.2 w. another standard to be applied to external power supplies in the coming years is the doe (department of energy) recommendation, whose active mode efficiency requirement for the same power throughput is 76.6%. if the ic is externally biased, the presented demonstration board is compliant with both standards, as can be seen from figure 21 , where the average efficiencies of the board at 115 v ac (81.6%) and at 230 v ac (77.2%) are plotted with dotted lines, together with the above limits. in the same figure the efficiency at 25%, 50%, 75% and 100% of output load for both input voltages is also shown. figure 21. active mode efficiency of the demonstration board and comparison with energy efficiency standards (ic externally biased) table 5. output voltage ripple at no/light load v in [v ac ] v out [mv] no load 25 ma load 90 2 7 115 2 7 230 4 8 265 4 9 am1 33 42v1 65 67 69 71 7 3 75 77 79 8 1 83 8 5 0.2 0.4 0.6 0. 8 1 eff [ % ] io u t [ % i out ] 115 2 3 0 a v @ 115 v a c a v @ 2 3 0 v a c doe limit coc4 limit
testing the board AN4164 16/38 doc id 023660 rev 1 5.5 light load performance the input power of the converter has been measured in no load condition for different input voltages and the results are reported in ta b l e 6 . in version 4 of the code of conduct, also the power consumption of the power supply when it is no loaded is considered. the criteria to be compliant with are reported in the table below: the performance of the presented board (when the self-biasing function is not used) is much better than required; the power consumption is more than ten times lower than the limit fixed by version 4 of the code of conduct. even though the performance seems to be disproportionally better than requirements, it is worth noting that often ac-dc adapter or battery charger manufacturers have very strict requirements about no load consumption and if the converter is used as an auxiliary power supply, the line filter is often the big line filter of the entire power supply that increases greatly the standby consumption. even though version 4 of the code of conduct does not have other requirements regarding light load performance, in order to give a more complete overview we report the input power and efficiency of the demonstration board also in two other light load cases. ta b l e 8 and ta b l e 9 show the performance when the output load is 25 mw and 50 mw respectively. table 6. no load input power v in [v ac ] p in [mw] ic externally biased ic self-biased 90 17.6 108 115 18.9 138 150 20.9 179 180 23.1 214 230 26.9 275 265 30.2 317 table 7. energy consumption criteria for no load nameplate output power (p no ) maximum power in no load for ac-dc eps 0 w p no 50 w < 0.3 w 50 w < p no < 250 w < 0.5 w
AN4164 testing the board doc id 023660 rev 1 17/38 the input power vs. input voltage for no load and light load condition ( ta b l e 6 , 8 and 9 ) is shown in the figures below. table 8. light load performance p out =25 mw v in [v ac ]p out [mw] p in [mw] efficiency (%) ic externally biased ic self-biased ic externally biased ic self-biased 90 25 49.7 128 50.30 19.6 115 25 51.5 157 48.54 15.9 150 25 54.7 200 45.70 12.5 180 25 57.3 236 43.63 10.6 230 25 61.7 296 40.52 8.4 265 25 64.8 337 38.58 7.4 table 9. light load performance p out =50 mw v in [v ac ]p out [mw] pin [mw] efficiency (%) ic externally biased ic self-biased ic externally biased ic self-biased 90 50 82.4 167 60.71 29.94 115 50 85.0 198 58.82 25.25 150 50 89.3 242 55.99 20.66 180 50 93.0 280 53.76 17.86 230 50 98.0 341 51.02 14.66 265 50 101.1 384 49.46 13.02 figure 22. p in vs. v in at no load and light load; ic externally biased (j1 selected) figure 23. p in vs. v in at no load and light load, ic self-biased (j1 not selected) am1154 3 v1 0 50 100 150 200 8 01051 3 01551 8 02052 3 0255 p in [mw] v in [v ac ] 0 25mw 50mw am11544v1 0 50 100 150 200 250 3 00 3 50 400 8 01051 3 01551 8 02052 3 0 255 p in [mw] v in [v ac ] 0 25mw 50mw
testing the board AN4164 18/38 doc id 023660 rev 1 depending on the equipment supplied, it?s possible to have several criteria to measure the standby or light load performance of a converter. one criterion is the measurement of the output power when the input power is equal to one watt. in ta b l e 1 0 the output power needed to have 1 w of input power in a different line conditions is given. figure 24 and 25 show the diagram of the output powers corresponding to p in = 1 w for different values of the input voltage. another requirement (eup lot 6) is that the input power should be less than 500 mw when the converter is loaded with 250 mw. the performances are shown in figure 26 for external biasing and in figure 27 for self biasing. in the former case the converter can satisfy even this requirement. table 10. p out @ p in =1 w v in [v ac ]p in [w] p out [w] efficiency (%) ic externally biased ic self-biased ic externally biased ic self-biased 90 1 0.78 0.64 78 64 115 1 0.77 0.60 77 60 150 1 0.73 0.55 73 55 180 1 0.70 0.49 70 49 230 1 0.68 0.43 68 43 265 1 0.65 0.40 65 40 figure 24. efficiency at p in = 1 w; ic externally biased (j1 selected) figure 25. efficiency at p in = 1 w; ic self biased (j1 not selected) am11545v1 40 45 50 55 60 65 70 75 8 0 8 0 110 140 170 200 2 3 0260 eff [ % ] v in [v ac ] am11546v1 3 5 40 45 50 55 60 65 70 75 8 0 8 0 110 140 170 200 2 3 0260 eff [ % ] v in [v ac ]
AN4164 testing the board doc id 023660 rev 1 19/38 figure 26. p in at p out = 250 mw; ic externally biased (j1 selected) figure 27. p in at p out = 250 mw; ic self biased (j1 not selected) am1 3 10 8 v1 0.25 0. 3 0. 3 5 0.4 0.45 0.5 8 0 110 140 170 200 2 3 0260 p in [w] v in [v ac ] am1 3 10 8 v1 0.25 0. 3 0. 3 5 0.4 0.45 0.5 8 0 110 140 170 200 2 3 0260 p in [w] v in [v ac ] am1 3 109v1 0.25 0. 3 0. 3 5 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0. 8 8 0 110 140 170 200 2 3 0260 p in [w] v in [v ac ]
functional check AN4164 20/38 doc id 023660 rev 1 6 functional check 6.1 soft-start at startup, the current limitation value reaches idlim after an internally fixed time, t ss , whose typical value is 8.5 msec. this time is divided into 16 time intervals, each corresponding to a current limitation step progressively increasing. in this way the drain current is limited during the output voltage increase, therefore reducing the stress on the secondary diode. the soft-start phase is shown in figure 28 and 29 . 6.2 overload protection in the case of overload or short-circuit (see figure 30 ), the drain current reaches the idlim value (or the one set by the user through the rlim resistor). in every cycle where this condition is met, a counter is incremented; if it is maintained continuously for the time t ovl (50 msec typical, internally fixed), the overload protection is tripped, the power section is turned off and the converter is disabled for a t restart time (1 second typ.). after this time has elapsed, the ic resumes switching and, if the short is still present, the protection occurs indefinitely in the same way ( figure 31 ). this ensures restart attempts of the converter with low repetition rate, so that it works safely with extremely low power throughput and avoids the ic overheating in the case of repeated overload events. furthermore, every time the protection is tripped, the internal soft-startup function is invoked ( figure 32 ), in order to reduce the stress on the secondary diode. after the short removal, the ic resumes normal working. if the short is removed during t ss or t ovl , i.e. before the protection tripping, the counter is decremented on a cycle-by-cycle basis down to zero and the protection is not tripped. if the short-circuit is removed during t restart , the ic must wait for the t restart period to elapse before switching is resumed ( figure 33 ). figure 28. soft-start @ startup figure 29. soft-start @ startup (zoom) am1 3 094v1 am1 3 095v1
AN4164 functional check doc id 023660 rev 1 21/38 6.3 feedback loop failure protection this protection is available any time the ic is not self-biased. as the loop is broken (rfbl shorted or rfbh open), the output voltage v out increases and the viper06 runs at its maximum current limitation. the v dd pin voltage increases as well, because it is linked to the v out voltage either directly or through the auxiliary winding, depending on the cases. if the v dd voltage reaches the v ddclamp threshold (23.5 v min.) in less than 50 msec, the ic is shut down by open loop failure protection (see figure 34 and 35 ), otherwise by olp, as described in the previous section. the breaking of the loop has been simulated by shorting the low-side resistor of the output voltage divider, rfbl = rfbl1+rfbl2. the same behavior can be induced opening the high-side resistor, rfbh = rfbh1+rfbh2. figure 30. olp short-circuit applied: olp tripping figure 31. output short-circuit maintained: olp steady-state am1 3 096v1 normal operation output is shorted here am1 3 097v1 t restart figure 32. output short-circuit maintained: olp steady-state (zoom) figure 33. output short-circuit removal and converter restart am1 3 09 8 v1 t restart t ovl t ss am1 3 099v1 output short is removed here t restart normal operation
functional check AN4164 22/38 doc id 023660 rev 1 the protection acts in auto-restart mode with t restart = 1sec ( figure 35 ). as the fault is removed, normal operation is restored after the last t restart interval has been completed ( figure 37 ). figure 34. feedback loop failure protection: tripping figure 35. feedback loop failure protection: steady-state am1 3 20 3 v1 output short is removed here t restart normal operation fault is applied here normal operation v dd reaches v ddclamp < t ovl am1 3 204v1 t restart figure 36. feedback loop failure protection: steady-state, zoom figure 37. feedback loop failure protection: converter restart am1 3 205v1 < t ovl am1 3 206v1 t restart fault is removed here normal operation
AN4164 feedback loop calculation guidelines doc id 023660 rev 1 23/38 7 feedback loop calculation guidelines 7.1 transfer function the set pwm modulator + power stage is indicated with g1(f), while c(f) is the ?controller?, i.e. the network which is in charge to ensure the stability of the system. the mathematical expression of the power plant g1(f) is the following: equation 2 where v out is the output voltage, ipkp is the primary peak current, fp is the frequency of the pole due to the output load and fz the frequency of the zero due to the esr of the output capacitor: equation 3 equation 4 figure 38. control loop block diagram am115 8 2v1 ) fp j (1 ) , ( ) fz (1 v ) p 2 j (1 ) , ( ) z 2 (1 v = i v (f) g out out pk out 1 f vdc fsw ipkp f j f vdc fsw ipkp f j ? + ? ? + ? = ? ? ? + ? ? ? ? + ? = 2esr) + (r c 1 fp out out ? = esr c 2 1 fz out ? ? =
feedback loop calculation guidelines AN4164 24/38 doc id 023660 rev 1 the mathematical expression of the compensator c(f) is: equation 5 where: equation 6 equation 7 equation 8 are chosen in order to censure the stability of the overall system. gm = 2 ma/v (typical) is the viper06 transconductance. 7.2 compensation procedure the first step is to choose the pole and zero of the compensator and the crossing frequency, for instance: ? fzc = fp/2 ? fpc = fz ? fcross = fcross_sel fsw/10 g1(fcross_sel) can be calculated from equation ( 2 ) and, since by definition it is | c(fcross_sel)*g1(fcross_sel)| = 1, c 0 , can be calculated as follows: equation 9 () ? ? ? ? ? ? ? ?? + ? ? ? ? ? + ? = = fpc j f j f fzc j f h c v i f c comp out 1 2 1 0 pk rfbh rfbl rfbl cp cc gm co + ? + ? = cc rc fzc ? ? ? = 2 1 cp cc rc cp cc fpc ? ? ? ? + = 2 ) _ ( 1 _ 1 _ 1 _ 2 0 sel f cross g h fzc j sel fcross fpc j sel f cross j sel f cross c comp ? ? + ? + ? ? ? ? =
AN4164 feedback loop calculation guidelines doc id 023660 rev 1 25/38 at this point the bode diagram of g1(f)*c(f) can be plotted, in order to check the phase margin for the stability. if the margin is not high enough, another choice for fzc, fpc and fcross_sel should be made, and the procedure repeated. when the stability is ensured, the next step is to find the values of the schematic components, which can be calculated, using the above formulas, as follows: equation 10 equation 11 equation 12 equation 13 1 3 . 3 ? = v vout rfbh rfbl rfbh rfbl rfbl c gm fpc fzc cp + ? ? = 0 ? ? ? ? ? ? ? ? ? ? = 1 fzc fpc cp cc cp cc fpc cp cc rc ? ? ? ? + = 2
thermal measurements AN4164 26/38 doc id 023660 rev 1 8 thermal measurements a thermal analysis of the demonstration board in full load condition at t amb = 25 c, both with and without the self-biasing function, has been performed using an ir camera. the results are shown in the following figures. when the self-biasing function is used the viper06 temperature is higher, due to the power dissipated by the hvstartup generator. figure 39. thermal measurement at v in = 90 v ac , full load, ic externally biased figure 40. thermal measurement at v in = 115 v ac , full load, ic externally biased am1 33 4 3 v1 am1 33 44v1
AN4164 thermal measurements doc id 023660 rev 1 27/38 figure 41. thermal measurement at v in = 230 v ac , full load, ic externally biased figure 42. thermal measurement at v in = 265 v ac , full load, ic externally biased figure 43. thermal measurement at v in = 90 v ac , iout = 310 ma, ic self biased am1 33 45v1 am1 33 46v1 am1 33 47v1
thermal measurements AN4164 28/38 doc id 023660 rev 1 figure 44. thermal measurement at v in = 115 v ac , iout = 310 ma, ic self biased figure 45. thermal measurement at v in = 230 v ac , full load, ic self biased figure 46. thermal measurement at v in = 265 v ac , full load, ic self biased am1 33 4 8 v1 am1 33 49v1 am1 33 50v1
AN4164 emi measurements doc id 023660 rev 1 29/38 9 emi measurements a pre-compliance test to the en55022 (class b) european normative has been performed using an emc analyzer and an lisn. average measurements are reported in the following figures. figure 47. average measurements at full load, t amb =25 c, 115 v ac , ic externally biased figure 48. average measurements at full load, t amb =25 c, 230 v ac , ic externally biased am1 33 51v1 am1 33 52v1
board layout AN4164 30/38 doc id 023660 rev 1 10 board layout figure 49. board layout - complete figure 50. board layout - top layer + top overlay am1 333 9v1 am1 33 40v1
AN4164 board layout doc id 023660 rev 1 31/38 figure 51. board layout - bottom layer + top overlay am1 33 41v1
conclusions AN4164 32/38 doc id 023660 rev 1 11 conclusions the viper06 allows a non-isolated converter to be designed in a simple way and with few external components. in this document a flyback has been described and characterized. special attention has been given to light load performance. the efficiency performance has been compared to the requirements of the code of conduct (version 4) for an external ac- dc adapter with very good results, the measured active mode efficiency is always higher with respect to the minimum required.
AN4164 test equipment and measurement of efficiency and light load performance doc id 023660 rev 1 33/38 appendix a test equipment and measurement of efficiency and light load performance the converter input power has been measured using a wattmeter. the wattmeter measures simultaneously the converter input current (using its internal ammeter) and voltage (using its internal voltmeter). the wattmeter is a digital instrument so it samples the current and voltage and converts them to digital form. the digital samples are then multiplied giving the instantaneous measured power. the sampling frequency is in the range of 20 khz (or higher depending on the instrument used). the display provides the average measured power, averaging the instantaneous measured power in a short period of time (1 second typ.). figure 52 shows how the wattmeter is connected to the uut (unit under test) and to the ac source and the wattmeter internal block diagram. an electronic load has been connected to the output of the power converter (uut), allowing to set and measure the converter's load current, while the output voltage has been measured by a voltmeter. the output power is the product between load current and output voltage. the ratio between the output power, calculated as previously stated, and the input power, measured by the wattmeter, is the converter's efficiency, which has been measured in different input/output conditions. a.1 measuring input power with reference to figure 52 , the uut input current causes a voltage drop across the ammeter's internal shunt resistance (the ammeter is not ideal as it has an internal resistance higher than zero) and across the cables connecting the wattmeter to the uut. if the switch of figure 52 is in position 1 (see also the simplified scheme of figure 53 ), this voltage drop causes an input measured voltage higher than the input voltage at the uut input that, of course, affects the measured power. the voltage drop is generally negligible if the uut input current is low (for example when measuring the input power of uut in light load condition). figure 52. connection of the uut to the wattmeter for power measurements am1 3 105v1 a v di s play x avg watt meter 1 2 ac s ource u.u.t (unit under te s t) input m u ltiplier voltmeter ammeter output + s witch am1 3 105v1 a v di s play x avg watt meter 1 2 ac s ource u.u.t (unit under te s t) input m u ltiplier voltmeter ammeter output + s witch
test equipment and measurement of efficiency and light load performance AN4164 34/38 doc id 023660 rev 1 in the case of high uut input current (i.e. for measurements in heavy-load conditions), the voltage drop can be relevant compared to the uut real input voltage. if this is the case, the switch in figure 52 can be changed to position 2 (see simplified scheme of figure 54 ) where the uut input voltage is measured directly at the uut input terminal and the input current does not affect the measured input voltage. on the other hand, the position of figure 54 may introduce a relevant error during light load measurements, when the uut input current is low and the leakage current inside the voltmeter itself (which is not an ideal instrument and doesn't have infinite input resistance) is not negligible. this is the reason why it is recommended to use the setting of figure 53 for light load measurements and figure 54 for heavy load measurements. if it is not clear which measurement scheme has the lesser effect on the result, try with both and register the lower input power value. as noted in iec 62301, instantaneous measurements are appropriate when power readings are stable. the uut is operated at 100% of nameplate output current for at least 30 minutes (warm-up period) immediately prior to conducting efficiency measurements. after this warm- up period, the ac input power is monitored for a period of 5 minutes to assess the stability of the uut. if the power level does not drift by more than 5% from the maximum value figure 53. switch in position 1 - setting for standby measurements figure 54. switch in position 2 - setting for efficiency measurements am1 3 106v1 v + - a ~ ac s ource uut u.u.t. ac input voltmeter ammeter w a ttmeter am1 3 107v1 v + - ~ ac s ource uut u.u.t. ac input voltmeter ammeter a w a ttmeter
AN4164 test equipment and measurement of efficiency and light load performance doc id 023660 rev 1 35/38 observed, the uut can be considered stable and the measurements can be recorded at the end of the 5-minute period. if ac input power is not stable over a 5-minute period, the average power or accumulated energy is measured over time for both ac input and dc output. some wattmeter models allow the measured input power to be integrated in a time range and then the energy absorbed by the uut to be measured during the integration time. the average input power is calculated by dividing it by the integration time itself.
references AN4164 36/38 doc id 023660 rev 1 12 references 1. code of conduct on energy efficiency of external power supplies, version 4 2. viper06 datasheet
AN4164 revision history doc id 023660 rev 1 37/38 13 revision history table 11. document revision history date revision changes 08-feb-2013 1 initial release.
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